The present invention relates to digital logic and memory circuits, and more particularly, to logic gate circuits and to latch circuits formed in a monolithic integrated circuit chip which is subject to charge generating disturbances.
Monolithic integrated circuit structural features have been shrinking rapidly in size in recent years. Along with this shrinkage, electrical currents and electrical charge accumulations formed and manipulated in integrated circuits based on these features have also been diminishing in value. As a result, charge accumulation quantities generated by certain charge generating disturbances which, in integrated circuits with larger feature sizes, would not be a problem are now quantities which are sufficiently large to cause difficulties in smaller feature integrated circuits.
In voltage level state switching circuits, such as logic circuits or memory circuits, which are constructed using such smaller integrated circuit structures, these disturbance charges can be sufficient to cause switching from an existing logic state to another at points in the circuit where such charge is generated. As an example, consider a typical inverter circuit in the complementary metal-oxide-semiconductor field-effect transistor (CMOS FET) logic circuit family implemented in a monolithic integrated circuit formed by advance, but now currently available, technology capable of providing features having a minimum lateral dimension on the order of 1.25 m. Such an inverter has a p-channel transistor drain connected to an n-channel transistor drain to form the inverter output with the gates of each connected together to form the inverter input. Assuming circuit component structural features of minimum size, the structure from the output of a preceding logic gate circuit, connected to the inverter input, through the gate structures of the inverter input could be expected to have stored in the parasitic capacitance associated therewith a quantity of charge having a value on the order of 0.5 pC.
Then, if the inverter is assumed to have a switching threshold voltage which is approximately half the inverter circuit supply voltage, any charge disturbance which is on the order of 0.25 pC is potentially sufficient to cause a change of voltage state in the inverter. In comparison, the charge which can be collected at a pn junction in the logic gate output structure subjected to impingement of an energetic heavy ion could be as much as to be on the order of 3.0 pC. Thus, a significant risk exists of an unwanted output voltage state change for such an inverter, representing an erroneous logic signal, where this inverter is fabricated using the technology now becoming available.
Typically, such disturbances are local to the region near where the disturbance is generated and are temporary; thus, such a disturbance is often termed a "single event upset." Also, though the disturbance cause may be temporary, the results of the disturbance may be stored and are subject to being propagated further in the system which may lead to longer term and more significant effects.
A typical source of such charge generating disturbances is particle radiation. Such particles impinging on a monolithic integrated circuit will have "interactions" with the semiconductor material lattice structure and electrons along the paths thereof through the integrated circuit semiconductor material. This will result in raising the energy of the electrons involved into the conduction band and leaving corresponding holes in the valance band. Should such electron-hole pairs be generated sufficiently close to a semiconductor pn junction, the electrons and holes so situated are subject to being collected by the action of electric fields in the region resulting because of voltage being supplied to such junction and because of diffusion toward such junction. The structure of transistor devices in monolithic integrated circuits, and the method of operating both such devices and the circuits using them generally, is such that only reverse-biased pn junctions need to be considered to understand the effects of a radiation particle impinging thereabout.
In FIG. 1, a semiconductor material substrate, 10, of one conductivity type is shown having in it a dopant diffusion or implantation forming a region, 11, of an opposite conductivity type. Should a radiation particle impinge on region 11 and pass on into remaining portions of substrate 10, electron-hole pairs will be generated along the track of the particle as a result of the "interactions" indicated above.
If substrate 10 is of p-type conductivity and region 11 is of n-type conductivity, a voltage applied to place region 11 positive with respect to remaining portions of substrate 10 leads to reverse-biasing the semiconductor pn junction, 12, therebetween. The electrons sufficiently energized by the radiation particle and the corresponding holes will be separated by the electric field near junction 12 with electrons being attracted to positive region 11 and holes being attracted or repelled into remaining portions of substrate 10. This separation of electrons and holes, in effect, provides a temporary current flow from region 11 into remaining portions of substrate 10.
This current will be comprised of an immediate drift current component for electrons and holes which are immediately subject to such electric fields. A further component of this current will be provided by those electrons and holes which subsequently, by diffusion, move to be within the influence of this electric field. Such a current flow would have the effect of tending to discharge region 11 and so reduce the voltage of region 11 with respect to region 10, and to discharge the parasitic capacitances unavoidably present across junction 12.
If the conductivity types of region 11 and substrate 10 were reversed, the voltage polarity would also have to be reversed to provide reverse-bias to junction 12. Upon a similar radiation particle impact, the same collection process would occur but region 11, rather than tending to be discharged by arriving electrons, would not tend to be charged by arriving holes and to increase in voltage with respect to substrate 10. However, in either situation, the charge generated by an impinging radiation particle would act in a manner to tend to reduce the reverse-bias voltage across pn junction 12.
Metal-oxide-semiconductor field-effect transistor (MOSFET) circuits using only n-channel field-effect transistors will have only regions such as 11 of solely n-type conductivity formed in a p-type conductivity substrate. In these circumstances, an impinging radiation particle will generate charge resulting in the electrons being attracted to the implanted or diffused regions serving as the sources and drains of the n-channel transistors. This charge, as stated above, tends to reduce the reverse-bias voltage on the associated pn-junction.
In those MOSFET circuits using only p-channel field-effect transistors, the implanted or diffused regions will be all p-type conductivity formed in an n-type conductivity substrate and will tend to increase in voltage as holes are attracted thereto as a result of the impingement of a radiation particle. CMOS FET requires further consideration as such circuits use both n-channel and p-channel field-effect transistors therein.
Such consideration can be given by looking further at FIG. 1 where a well region, 13, is shown formed in substrate 10 having a further dopant implanted or diffused region, 14, formed therein. Well region 13 is separated from substrate 10 by semiconductor pn junction, 15, and region 14 is separated from well region 13 by a further semiconductor pn junction, 16. If an n-well CMOS arrangement is contemplated, then well region 13 is of n-type conductivity as would region 11 be. Substrate 10 would then be of p-type conductivity as would region 14.
Regions 11 and 14 are then typical of the kinds of region used as sources and drains in constructing n-channel and p-channel field-effect transistors in an n-well CMOS integrated circuit. In such a circuit, junctions 12, 15 and 16 will all be reverse-biased in operation. This means that region 11 would be held positive with respect to substrate 10 as would region 13. Region 13 would also be held positive with respect to region 14.
A radiation particle impinging on region 11 and continuing into substrate 10 would still yield the same results as described above. That is, the electrons generated by the impinging particle would be attracted to region 11, and would be attracted from some distance into substrate 10, perhaps on the order of 7 .mu.m in a current advanced fabrication process, and somewhat less in smaller structure fabrication processes of the future. This would again tend to discharge region 11 and to reduce the reverse-bias voltage on junction 12.
A radiation particle impinging on region 14 and continuing on through region 13 into substrate 10 would, on the other hand, lead to much less charging of region 14 by holes on a comparable basis. The holes generated in region 13 by the radiation particle would split into two categories with those sufficiently near junction 16 being attracted to region 14, but with those sufficiently near junction 15 being attracted to substrate 10. As a result, region 14 will only attract holes which are within 1 to 2 .mu.m of junction 16 in well region 13. (This is true of current advance fabrication processes and is equal to approximately one half the distance separating junctions 15 and 16.) Further, the lower mobility of holes in well region 13 will also diminish the number of them which are attracted to region 14.
As a result, for n-well CMOS monolithic integrated circuits, the charging of p-type conductivity sources and drains will be relatively insignificant. Instead, the discharging of the n-type conductivity sources and drains of the n-channel field-effect transistors will be most signficant in causing voltage changes sufficient to upset circuit operation. The p-type conductivity sources and drains of the p-channel field-effect transistors will attract charge from such a particle impinging therein which, in quantity, will typically be in order of magnitude less than the charge attracted by the n-type conductivity sources and drains. Thus, any voltage changes on such p-type conductivity sources and drains (because of this attracted charge) will be smaller also by an order of magnitude. The p-well CMOS integrated circuits, on the other hand, the charge attracted to the p-type conductivity sources and drains resulting from an impinging radiation particle will be more dominant compared to the charge attracted to the n-type conductivity sources and drains.
Returning to the earlier example of the common CMOS circuit inverter, consider this inverter having connected to its input a NAND or NOR logic gate of the basic configuration commonly used in CMOS circuits, both of which are fabricated in an n-well fabrication process. If such a logic gate has its single output terminating region which is in a high voltage level state, one or more of the p-channel transistors in the gate connected to the output will be switched into the "on" or conducting condition while one or more of the n-channel transistors connected to the output will be switched into the "off" or nonconducting condition.
In this circumstance, the power supply voltage is essentially applied as a reverse-bias voltage across the drain or drains of these off n-channel transistors. The impingement of a radiation particle in one of these n-channel transistor drain regions would generate a charge perhaps on the order of 3.0 pC, as earlier indicated, which would tend to reduce the reverse bias on the drain junction. Thus, this charge accumulated in the drain region would temporarily but drastically lower the voltage at the output of the logic gate and so the voltage applied to the input of the inverter. A similar result would follow if another such NAND or NOR logic gate was substituted for the inverter.
There is nothing which would prevent such a change at the input of the inverter from changing the output state of the inverter to the opposite state. This could similarly be true of the logic gate depending on the values taken by other input variables. Such an erroneous logic state change could then propagate along the subsequent logic circuits connected to the output of either such inverter or such a logic gate. This, of course, assumes that the inverter, or the logic gate is used instead, and the subsequent logic circuits could respond sufficiently fast to the rapidity of the voltage state change, and that the configuration of the subsequent logic circuits and the state of the other logical variables applied thereto would not serve to block such a propagation.
Clearly, however, in many instances such a propagation would not be blocked with the consequence of erroneous system operation. Further, such a change could occur in one of a pair of cross-coupled inverters serving as a data latch leading to incorrect data being stored in the system. Such data could affect a number of future system operations possibly causing some of them to provide erroneous system results.
Therefore, logic gates circuit arrangements which would lead to logic systems that avoid the undesirable consequences of charge generating disturbances, such as by radiation particle impingement, would be desirable. Also desirable would be the provision of latch circuits or other data storing circuits which would be unaffected by such charge generating disturbances.